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H
40 ns Prop. Delay, SO-8 Optocoupler Technical Data
HCPL-0710
Features
* +5 V CMOS Compatibility * 8 ns max. Pulse Width Distortion * 20 ns max. Prop. Delay Skew * High Speed: 12 Mbd * 40 ns max. Prop. Delay * 10 kV/s Minimum Common Mode Rejection * 0C to 85C Temp. Range * Safety and Regulatory Approvals UL Recognized 2500 V rms for 1 min. per UL 1577 CSA Component Acceptance Notice #5
Description
Available in the SO-8 package style, the HCPL-0710 optocoupler utilizes the latest CMOS IC technology to achieve outstanding performance with very low power consumption. The HCPL-0710 requires only two bypass capacitors for complete CMOS compatability.
Basic building blocks of the HCPL-0710 are a CMOS LED driver IC, a high speed LED and a CMOS detector IC. A CMOS logic input signal controls the LED driver IC which supplies current to the LED. The detector IC incorporates an integrated photodiode, a high-speed transimpedance amplifier, and a voltage comparator with an output driver.
Functional Diagram
**VDD1
1
8
VDD2**
Applications
* Digital Fieldbus Isolation: DeviceNet, SDS, Profibus * AC Plasma Display Panel Level Shifting * Multiplexed Data Transmission * Computer Peripheral Interface * Microprocessor System Interface
VI
2 IO
7
NC*
*
3 LED1
6
VO
GND1
4 SHIELD
5
GND2
TRUTH TABLE (POSITIVE LOGIC) VI, INPUT H L LED1 OFF ON VO, OUTPUT H L
*Pin 3 is the anode of the internal LED and must be left unconnected for guaranteed data sheet performance. Pin 7 is not connected internally. External connections to pin 7 are not recommended. **A 0.1 F bypass capacitor must be connected between pins 1 and 4, and 5 and 8. CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD.
Ordering Information
Specify Part Number followed by Option Number (if desired) Example HCPL-0710#XXX No Option = Standard SO-8 package, 100 per tube. 500 = Tape and Reel Packaging Option, 1500 per reel. Option data sheets available. Contact Hewlett-Packard sales representative or authorized distributor.
Package Outline Drawing
8 7 6 710 YWW 5 5.842 0.203 (0.236 0.008)
3.937 0.127 (0.155 0.005)
TYPE NUMBER (LAST 3 DIGITS) 2 3 4 1.270 BSG (0.050) 5.080 0.005 (0.200 0.005) 7 45 X 0.432 (0.017) DATE CODE
0.381 0.076 (0.016 0.003)
PIN 1 ONE
3.175 0.127 (0.125 0.005)
1.524 (0.060) 0.152 0.051 (0.006 0.002)
0.228 0.025 (0.009 0.001)
DIMENSIONS IN MILLIMETERS AND (INCHES). LEAD COPLANARITY = 0.10 mm (0.004 INCHES).
0.305 MIN. (0.012)
Solder Reflow Thermal Profile
260 240 220 200 180 160 140 120 100 80 60 40 20 0 0 1 2 3 4 5 6 7 8 9 10 11 12 T = 145C, 1C/SEC T = 115C, 0.3C/SEC
TEMPERATURE - C
T = 100C, 1.5C/SEC
TIME - MINUTES (NOTE: USE OF NON-CHLORINE ACTIVATED FLUXES IS RECOMMENDED.)
Regulatory Information
The HCPL-0710 has been approved by the following organizations:
UL Recognized under UL 1577, component recognition program, File E55361.
CSA Approved under CSA Component Acceptance Notice #5, File CA 88324.
Insulation and Safety Related Specifications
Parameter Minimum External Air Gap (Clearance) Minimum External Tracking (Creepage) Minimum Internal Plastic Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Isolation Group Symbol L(I01) L(I02) Value Units 4.9 mm 4.8 0.08 mm mm Conditions Measured from input terminals to output terminals, shortest distance through air. Measured from input terminals to output terminals, shortest distance path along body. Insulation thickness between emitter and detector; also known as distance through insulation. DIN IEC 112/VDE 0303 Part 1 Material Group (DIN VDE 0110, 1/89, Table 1)
CTI
200 IIIa
Volts
Absolute Maximum Ratings
Parameter Storage Temperature Ambient Operating Temperature[1] Supply Voltages Input Voltage Output Voltage Average Output Current Lead Solder Temperature Solder Reflow Temperature Profile Symbol Min. Max. Units Figure TS -55 125 C TA -40 +100 C VDD1, VDD2 0 5.5 Volts VI -0.5 VDD1 +0.5 Volts VO -0.5 VDD2 +0.5 Volts IO 10 mA 260C for 10 sec., 1.6 mm below seating plane See Solder Reflow Temperature Profile Section
Recommended Operating Conditions
Parameter Ambient Operating Temperature Supply Voltages Logic High Input Voltage Logic Low Input Voltage Input Signal Rise and Fall Times Symbol TA VDD1, VDD2 VIH VIL tr, tf Min. 0 4.5 0.8 * VDD1 0.0 Max. +85 5.5 VDD1 0.8 1.0 Units C V V V ms Figure
1, 2
Electrical Specifications
Test conditions that are not specified can be anywhere within the recommended operating range. All typical specifications are at TA = +25C, VDD1 = VDD2 = +5 V. Parameter Symbol IDD1L IDD1H IDD1 IDD2 II VOH VOL Min. Typ. 6.0 1.5 Max. Units 10.0 3.0 13.0 11.0 10 mA mA mA mA A V V Test Conditions VI = 0 V VI = VDDI Fig. Note 2
DC Specifications
Logic Low Input Supply Current Logic High Input Supply Current Input Supply Current Output Supply Current Input Current Logic High Output Voltage Logic Low Output Voltage
5.5 -10 VDD2 - 0.1 VDD2 0.8 *VDD2 VDD2 - 0.5 0 0.5 20 23 80 3
0.1 1.0 40 40
IO = -20 A, VI = VIH 1, 2 IO = -4 mA, VI = VIH IO = 20 A, VI = VIL IO = 4 mA, VI = VIL CL = 15 pF CMOS Signal Levels 3, 7 3
Switching Specifications
Propagation Delay Time tPHL to Logic Low Output Propagation Delay Time tPLH to Logic High Output Pulse Width PW Data Rate Pulse Width Distortion PWD |tPHL - tPLH| Propagation Delay Skew tPSK Output Rise Time tR (10 - 90%) Output Fall Time tF (90 - 10%) Common Mode |CMH| Transient Immunity at Logic High Output Common Mode |CML| Transient Immunity at Logic Low Output Input Dynamic Power CPD1 Dissipation Capacitance Output Dynamic Power CPD2 Dissipation Capacitance ns
4 12.5 8 20 9 8 CL = 15 pF CMOS Signal Levels 5, 9 6, 10 kV/s VI = VDD1, VO > 0.8 VDD1, VCM = 1000 V VI = 0 V, VO > 0.8 V, VCM = 1000 V pF 7 MBd ns CL = 15 pF CMOS Signal Levels 4, 8 5 6
10
20
10
20
60
8
10
Package Characteristics
Parameter Symbol Min. Input-Output Momentary VISO 2500 Withstand Voltage Resistance RI-O (Input-Output) Capacitance CI-O (Input-Output) Input Capacitance CI Input IC Junction-to-Case jci Thermal Resistance Output IC Junction-to-Case jco Thermal Resistance Package Power Dissipation PPD
Notes: 1. Absolute Maximum ambient operating temperature means the device will not be damaged if operated under these conditions. It does not guarantee functionality. 2. The LED is ON when VI is low and OFF when VI is high. 3. tPHL propagation delay is measured from the 50% level on the falling edge of the VI signal to the 50% level of the falling edge of the VO signal. tPLH propagation delay is measured from the 50% level on the rising edge of the VI signal to the 50% level of the rising edge of the VO signal. 4. Mimimum Pulse Width is the shortest pulse width at which 10% maximum, Pulse Width Distortion can be guaranteed. Maximum Data Rate is the inverse of Minimum Pulse Width. Operating the HCPL-0710 at data rates above 12.5 MBd is possible provided PWD and data dependent jitter increases and relaxed noise margins
Typ.
Max.
Units Vrms pF
1012 0.6 3.0 160 135 150
Test Conditions Fig. RH 50%, t = 1 min., TA = 25C VI-O = 500 Vdc f = 1 MHz
Note 9, 10, 11 9
12 C/W Thermocouple located at center underside of package
mW
are tolerable within the application. For instance, if the maximum allowable variation of bit width is 30%, the maximum data rate becomes 37.5 MBd. Please note that HCPL-0710 performance above 12.5 MBd is not guaranteed by Hewlett-Packard. 5. PWD is defined as |tPHL - tPLH|. %PWD (percent pulse width distortion) is equal to the PWD divided by pulse width. 6. tPSK is equal to the magnitude of the worst case difference in tPHL and/or tPLH that will be seen between units at any given temperature within the recommended operating conditions. 7. CMH is the maximum common mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common mode voltage slew rates apply to both rising and falling common mode voltage edges.
2.2
8. Unloaded dynamic power dissipation is calculated as follows: CPD * VDD2 * f + IDD * VDD, where f is switching frequency in MHz. 9. Device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together and pins 5, 6, 7, and 8 shorted together. 10. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage 3000 VRMS for 1 second (leakage detection current limit, II-O 5 A). 11. The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. For the continuous voltage rating refer to your equipment level safety specification or HP Application Note 1074 entitled "Optocoupler Input-Output Endurance Voltage." 12. CI is the capacitance measured at pin 2 (VI).
5 4
VO (V)
TPLH, TPHL (ns)
0 C 25 C 85 C
VITH (V)
2.1 2.0 1.9 1.8 1.7 1.6 4.5
0 C 25 C 85 C
29 27 25 23 21 19 17 TPHL TPLH
3 2 1 0
0
1
2 VI (V)
3
4
5
4.75
5 VDD1 (V)
5.25
5.5
15
0
10
20 30
40
50
60 70
80
TA (C)
Figure 1. Typical Output Voltage vs. Input Voltage.
Figure 2. Typical Input Voltage Switching Threshold vs. Input Supply Voltage.
Figure 3. Typical Propagation Delays vs. Temperature.
4
15
7
3
14
PWD (ns)
TR (ns)
6
2
TF (ns)
5
4
13
1
3
0
0
20
40 TA (C)
60
80
12
0
20
40 TA (C)
60
80
2
0
20
40 TA (C)
60
80
Figure 4. Typical Pulse Width Distortion vs. Temperature.
Figure 5. Typical Rise Time vs. Temperature.
Figure 6. Typical Fall Time vs. Temperature.
29 27
TPLH, TPHL (ns)
6 5 4
TR (ns)
25 23 21 19 17 15 13 11 9 7
25 23 21 19 17 15 0 5 10 15 20 25 30 35 TPLH TPHL
PWD (ns)
3 2 1 0
0
5
10
15
20
25
30
35
5
0
5
10
15
20
25
30
35
CI (pF)
CI (pF)
CI (pF)
Figure 7. Typical Propagation Delays vs. Output Load Capacitance.
Figure 8. Typical Pulse Width Distortion vs. Output Load Capacitance.
Figure 9. Typical Rise Time vs. Load Capacitance.
10 9 8
FALL TIME (ns)
7 6 5 4 3 2 1 0 0 5 10 15 20 25 30 35
CI (pF)
Figure 10. Typical Fall Time vs. Load Capacitance.
Application Information
Bypassing and PC Board Layout The HCPL-0710 optocoupler is extremely easy to use. No external interface circuitry is required because the HCPL-0710 uses high-speed CMOS IC
technology allowing CMOS logic to be connected directly to the inputs and outputs. As shown in Figure 11, the only external components required for proper operation are two bypass capacitors. Capacitor values should be between 0.01 F and
0.1 F. For each capacitor, the total lead length between both ends of the capacitor and the power-supply pins should not exceed 20 mm. Figure 12 illustrates the recommended printed circuit board layout for the HPCL-0710.
VDD1 C1 VI
1 2 NC 3 GND1 4
8 C2 7 NC 6 5 GND2
710 YYWW
VDD2
VO
C1, C2 = 0.01 F TO 0.1 F
Figure 11. Recommended Printed Circuit Board Layout.
VDD1 VI C1
VDD2
710 YYWW
C2 VO GND2 C1, C2 = 0.01 F TO 0.1 F
GND1
Figure 12. Recommended Printed Circuit Board Layout.
Propagation Delay, PulseWidth Distortion and Propagation Delay Skew
Propagation Delay is a figure of merit which describes how quickly a logic signal propagates through a system. The propaga-
tion delay from low to high (tPLH) is the amount of time required for an input signal to propagate to the output, causing the output to change from low to high. Similarly, the propagation delay from high to low (tPHL) is the
amount of time required for the input signal to propagate to the output, causing the output to change from high to low. See Figure 13.
INPUT VI tPLH OUTPUT VO 90% 10% tPHL 90%
5 V CMOS 50% 0V
10%
VOH 2.5 V CMOS VOL
Figure 13.
Pulse-width distortion (PWD) is the difference between tPHL and tPLH and often determines the maximum data rate capability of a transmission system. PWD can be expressed in percent by dividing the PWD (in ns) by the minimum pulse width (in ns) being transmitted. Typically, PWD on the order of 20 - 30% of the minimum pulse width is tolerable. The PWD specification for the HCPL-0710 is 8 ns (10%) maximum across recommended operating conditions. 10% maximum is dictated by the most stringent of the three fieldbus standards, PROFIBUS. Propagation delay skew, tPSK, is an important parameter to consider in parallel data applications where synchronization of signals
on parallel data lines is a concern. If the parallel data is being sent through a group of optocouplers, differences in propagation delays will cause the data to arrive at the outputs of the optocouplers at different times. If this difference in propagation delay is large enough it will determine the maximum rate at which parallel data can be sent through the optocouplers. Propagation delay skew is defined as the difference between the minimum and maximum propagation delays, either tPLH or tPHL, for any given group of optocouplers which are operating under the same conditions (i.e., the same drive current, supply voltage, output load, and operating
temperature). As illustrated in Figure 14, if the inputs of a group of optocouplers are switched either ON or OFF at the same time, tPSK is the difference between the shortest propagation delay, either tPLH or tPHL, and the longest propagation delay, either tPLH or tPHL. As mentioned earlier, tPSK can determine the maximum parallel data transmission rate. Figure 15 is the timing diagram of a typical parallel data application with both the clock and data lines being sent through the optocouplers. The figure shows data and clock signals at the inputs and outputs of the optocouplers. In this case the data is assumed to be clocked off of the rising edge of the clock.
VI
50% INPUTS
DATA
VO
2.5 V, CMOS tPSK
CLOCK
VI
50%
DATA OUTPUTS 2.5 V, CMOS CLOCK tPSK tPSK
VO
Figure 14. Propagation Delay Skew Waveform.
Figure 15. Parallel Data Transmission Example.
Propagation delay skew represents the uncertainty of where an edge might be after being sent through an optocoupler. Figure 15 shows that there will be uncertainty in both the data and clock lines. It is important that these two areas of uncertainty not overlap, otherwise the clock signal might arrive before all of the data outputs have settled, or
some of the data outputs may start to change before the clock signal has arrived. From these considerations, the absolute minimum pulse width that can be sent through optocouplers in a parallel application is twice tPSK. A cautious design should use a slightly longer pulse width to ensure that any additional
uncertainty in the rest of the circuit does not cause a problem. The HCPL-0710 optocoupler offers the advantage of guaranteed specifications for propagation delays, pulse-width distortion, and propagation delay skew over the recommended temperature and power supply ranges.
Digital Field Bus Communication Networks
To date, despite its many drawbacks, the 4 - 20 mA analog current loop has been the most widely accepted standard for implementing process control systems. In today's manufacturing environment, however, automated systems are expected to help
CONTROLLER
manage the process, not merely monitor it. With the advent of digital field bus communication networks such as DeviceNet, PROFIBUS, and Smart Distributed Systems (SDS), gone are the days of constrained information. Controllers can now receive multiple readings from field devices (sensors, actuators, etc.) in addition to diagnostic information.
The physical model for each of these digital field bus communication networks is very similar as shown in Figure 16. Each includes one or more buses, an interface unit, optical isolation, transceiver, and sensing and/or actuating devices.
BUS INTERFACE OPTICAL ISOLATION TRANSCEIVER FIELD BUS TRANSCEIVER OPTICAL ISOLATION BUS INTERFACE TRANSCEIVER OPTICAL ISOLATION BUS INTERFACE TRANSCEIVER OPTICAL ISOLATION BUS INTERFACE TRANSCEIVER OPTICAL ISOLATION BUS INTERFACE
XXXXXX
SENSOR
YYY
DEVICE CONFIGURATION MOTOR STARTER
MOTOR CONTROLLER
Figure 16. Typical Field Bus Communication Physical Model.
Optical Isolation for Field Bus Networks
To recognize the full benefits of these networks, each recommends providing galvanic isolation using Hewlett-Packard optocouplers. Since network communication is bi-directional (involving receiving data from and transmitting data onto the network), two Hewlett-Packard optocouplers are needed. By providing galvanic isolation, data integrity is retained via noise reduction and the elimination of
false signals. In addition, the network receives maximum protection from power system faults and ground loops. Within an isolated node, such as the DeviceNet Node shown in Figure 17, some of the node's components are referenced to a ground other than V- of the network. These components could include such things as devices with serial ports, parallel ports, RS232 and RS485 type ports. As shown in Figure 17, power from
the network is used only for the transceiver and input (network) side of the optocouplers. Isolation of nodes connected to any of the three types of digital field bus networks is best achieved by using the HCPL-0710 optocoupler. For each network, the HCPL-0710 satisifies the critical propagation delay and pulse width distortion requirements over the temperature range of 0C to +85C, and power supply voltage range of 4.5 V to 5.5 V.
AC LINE
NODE/APP SPECIFIC uP/CAN
LOCAL NODE SUPPLY
HCPL 0710
HCPL 0710 5 V REG.
GALVANIC ISOLATION BOUNDARY
TRANSCEIVER
DRAIN/SHIELD SIGNAL POWER V+ (SIGNAL) V- (SIGNAL) V+ (POWER) V- (POWER)
NETWORK POWER SUPPLY
Figure 17. Typical DeviceNet Node.
Implementing DeviceNet and SDS with the HCPL-0710
With transmission rates up to 1 Mbit/s, both DeviceNet and SDS are based upon the same broadcast-oriented, communications protocol -- the Controller Area Network (CAN). Three types of isolated nodes are recommended for use on these networks: Isolated Node Powered
by the Network (Figure 18), Isolated Node with Transceiver Powered by the Network (Figure 19), and Isolated Node Providing Power to the Network (Figure 20). Isolated Node Powered by the Network This type of node is very flexible and as can be seen in Figure 18, is regarded as "isolated" because not all of its components have the
same ground reference. Yet, all components are still powered by the network. This node contains two regulators: one is isolated and powers the CAN controller, nodespecific application and isolated (node) side of the two optocouplers while the other is nonisolated. The non-isolated regulator supplies the transceiver and the non-isolated (network) half of the two optocouplers.
NODE/APP SPECIFIC uP/CAN ISOLATED SWITCHING POWER SUPPLY REG. TRANSCEIVER GALVANIC ISOLATION BOUNDARY
HCPL 0710
HCPL 0710
DRAIN/SHIELD SIGNAL POWER V+ (SIGNAL) V- (SIGNAL) V+ (POWER) V- (POWER)
NETWORK POWER SUPPLY
Figure 18. Isolated Node Powered by the Network.
Isolated Node with Transceiver Powered by the Network Figure 19 shows a node powered by both the network and another source. In this case, the transceiver and isolated (network) side of the two optocouplers are
powered by the network. The rest of the node is powered by the AC line which is very beneficial when an application requires a significant amount of power. This method is also desirable as it does not heavily load the network.
More importantly, the unique "dual-inverting" design of the HCPL-0710 ensures the network will not "lock-up" if either AC line power to the node is lost or the node powered-off. Specifically, when input power (VDD1) to the HCPL-0710 located in the transmit path is eliminated, a RECESSIVE bus state is ensured as the HCPL-0710 output voltage (VO) goes HIGH.
AC LINE
NON ISO 5V NODE/APP SPECIFIC uP/CAN GALVANIC ISOLATION BOUNDARY REG. TRANSCEIVER
HCPL 0710
HCPL 0710
DRAIN/SHIELD SIGNAL POWER V+ (SIGNAL) V- (SIGNAL) V+ (POWER) V- (POWER)
NETWORK POWER SUPPLY
Figure 19. Isolated Node with Transceiver Powered by the Network.
Isolated Node Providing Power to the Network Figure 20 shows a node providing power to the network. The AC line powers a regulator which provides five (5) volts locally. The AC line also powers a 24 volt isolated supply, which powers the network, and another five-volt
regulator, which, in turn, powers the transceiver and isolated (network) side of the two optocouplers. This method is recommended when there are a limited number of devices on the network that don't require much power, thus eliminating the need for separate power supplies.
More importantly, the unique "dual-inverting" design of the HCPL-0710 ensures the network will not "lock-up" if either AC line power to the node is lost or the node powered-off. Specifically, when input power (VDD1) to the HCPL-0710 located in the transmit path is eliminated, a RECESSIVE bus state is ensured as the HCPL-0710 output voltage (VO) goes HIGH.
AC LINE
DEVICENET NODE NODE/APP SPECIFIC uP/CAN ISOLATED SWITCHING POWER SUPPLY 5 V REG. TRANSCEIVER GALVANIC ISOLATION BOUNDARY 5 V REG.
HCPL 0710
HCPL 0710
DRAIN/SHIELD SIGNAL POWER V+ (SIGNAL) V- (SIGNAL) V+ (POWER) V- (POWER)
Figure 20. Isolated Node Providing Power to the Network.
Power Supplies and Bypassing The recommended DeviceNet application circuit is shown in Figure 21. Since the HCPL-0710 is fully compatible with CMOS logic level signals, the optocoupler is connected directly to the
GALVANIC ISOLATION BOUNDARY
CAN transceiver. Two bypass capacitors (with values between 0.01 and 0.1 F) are required and should be located as close as possible to the input and output power-supply pins of the HCPL0710. For each capacitor, the
total lead length between both ends of the capacitor and the power supply pins should not exceed 20 mm. The bypass capacitors are required because of the high-speed digital nature of the signals inside the optocoupler.
ISO 5 V
5V 1 VDD1 VDD2 8 7 HCPL-0710 VO 6 GND2 5 + 0.01 F TxD VCC CANH 82C250 C4 0.01 F Rs 5 GND2 GND1 4 3 HCPL-0710 VIN 2 VDD1 1 5V 0.01 F GND CANL REF RXD D1 30 V C1 0.01 F 500 V R1 1M VREF + LINEAR OR SWITCHING REGULATOR + 5 V+ 4 CAN+ 3 SHIELD 2 CAN- 1 V-
TX0
2 VIN 3 4 GND1 GND
0.01 F
RX0
6 VO 7 8 VDD2
0.01 F
ISO 5 V
Figure 21. Recommended DeviceNet Application Circuit.
Implementing PROFIBUS with the HCPL-0710
An acronym for Process Fieldbus, PROFIBUS is essentially a twisted-pair serial link very similar to RS-485 capable of achieving high-speed communication up to 12 MBd. As shown in Figure 22, a PROFIBUS Controller (PBC) establishes the connec-
tion of a field automation unit (control or central processing station) or a field device to the transmission medium. The PBC consists of the line transceiver, optical isolation, frame character transmitter/receiver (UART), and the FDL/APP processor with the interface to the PROFIBUS user.
PROFIBUS USER: CONTROL STATION (CENTRAL PROCESSING) OR FIELD DEVICE
USER INTERFACE FDL/APP PROCESSOR UART PBC OPTICAL ISOLATION
TRANSCEIVER MEDIUM
Figure 22. PROFIBUS Controller (PBC).
Power Supplies and Bypassing
The recommended PROFIBUS application circuit is shown in Figure 23. Since the HCPL-0710 is fully compatible with CMOS logic level signals, the optocoupler is connected directly to the transceiver. Two bypass capacitors (with values between 0.01 and 0.1 F) are required and should be located as close as possible to the input and output
power-supply pins of the HCPL0710. For each capacitor, the total lead length between both ends of the capacitor and the power supply pins should not exceed 20 mm. The bypass capacitors are required because of the high-speed digital nature of the signals inside the optocoupler. Being very similar to multi-station RS485 systems, the HCPL-061N optocoupler provides a transmit disable function which is neces-
sary to make the bus free after each master/slave transmission cycle. Specifically, the HCPL061N disables the transmitter of the line driver by putting it into a high state mode. In addition, the HCPL-061N switches the RX/TX driver IC into the listen mode. The HCPL-061N offers HCMOS compatibility and the high CMR performance (1 kV/s at VCM = 1000 V) essential in industrial communication interfaces.
GALVANIC ISOLATION BOUNDARY ISO 5 V 8 VDD2 0.01 F Rx 7 HCPL-0710 6 VO 5 GND2 3 GND1 4 VDD1 1 VIN 2 0.01 F 0.01 F 4 2 ISO 5 V 1 VDD1 Tx 2 VIN HCPL-0710 0.01 F 3 4 GND1 VO 6 GND2 5 VDD2 8 7 0.01 F 5V D RE GND 5 0.01 F 1M 1 R 5V 5V
8 VCC A SN75176B B 7 6 RT - +
3 DE
5V 1 ISO 5 V 2 ANODE Tx ENABLE 1, 5 k 3 CATHODE 4 VE 7 0.01 F VO 6 GND 5 1 k VCC 8
HCPL-061N
Figure 23. Recommended PROFIBUS Application Circuit.
H
For technical assistance or the location of your nearest Hewlett-Packard sales office, distributor or representative call: Americas/Canada: 1-800-235-0312 or 408-654-8675 Far East/Australasia: Call your local HP sales office. Japan: (81 3) 3335-8152 Europe: Call your local HP sales office. Data subject to change. Copyright (c) 1997 Hewlett-Packard Co. Printed in U.S.A. 5965-6033E (1/97)

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